Complementary metal-oxide-semiconductor field effect transistor

Abstract

A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Claims

1. A complementary metal-oxide-semiconductor field effect transistor (CMOSFET), comprising: a substrate, having a first conductivity type; a first epitaxial layer, having the first conductivity type, and disposed on the substrate; a second epitaxial layer, having a second conductivity type, and disposed on the first epitaxial layer; a first sinker, having the second conductivity type, and disposed in the second epitaxial layer, wherein the first sinker extends from the first epitaxial layer to an upper surface of the second epitaxial layer, and the first sinker separates a first region from the second epitaxial layer; a second sinker, having the second conductivity type, and disposed in the second epitaxial layer, wherein the second sinker extends from the first epitaxial layer to the upper surface of the second epitaxial layer, and the second sinker separates a second region from the second epitaxial layer outside the first region; a well, having the first conductivity type, and disposed in the first region; a first transistor, disposed in the well; a second transistor, disposed in the second region; a first buried layer, having the second conductivity type, and disposed between the first region and the first epitaxial layer and connected to the first sinker; a second buried layer, having the second conductivity type, and disposed between the second region and the first epitaxial layer and connected to the second sinker; and a deep trench isolation, disposed between the first region and the second region, wherein the deep trench isolation extends from the substrate to the upper surface of the second epitaxial layer. 2. The CMOSFET of claim 1 , wherein a material of the deep trench isolation comprises dielectric material, polysilicon, doped polysilicon, metal or a titanium/titanium nitride/tungsten composite structure. 3. The CMOSFET of claim 1 , further comprising a metal silicide layer disposed between the deep trench isolation and the substrate. 4. The CMOSFET of claim 3 , wherein a material of the metal silicide layer comprises titanium silicide, nickel silicide, cobalt silicide or tungsten silicide. 5. The CMOSFET of claim 1 , wherein the first buried layer and the second buried layer have a dopant concentration greater than the dopant concentration of the second epitaxial layer. 6. The CMOSFET of claim 1 , wherein the first transistor and the second transistor comprise high voltage metal-oxide-semiconductor field effect transistor. 7. The CMOSFET of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type. 8. The CMOSFET of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of preventing latch-up. 2. Description of Related Art The design of a semiconductor device must continuously improve with the increasing level of integration and the increasingly complicated requirements. For example, the design of high-voltage devices must be strong enough to withstand high voltage operation while not affecting the operation of other devices. In the following, the problems and limitation of a conventional high voltage device is described with reference to FIG. 1 . FIG. 1 is a schematic cross-sectional view of a conventional high voltage device. The high voltage device is a complementary metal-oxide-semiconductor field effect transistor (CMOSFET) comprising two lateral double-diffused metal-oxide-semiconductor field effect transistors (LDMOSFET). As shown in FIG. 1 , the high voltage device includes a P-type substrate (P-sub) 100 , gates 102 and 104 , gate dielectric layers 106 and 108 , a P-well 112 p , a P-tub 114 p , doped regions 116 p , 118 p and 120 p , N-tubs 112 n and 124 n , doped regions 126 n , 128 n and 130 n , an isolation 134 , a dielectric layer 136 , interconnects 138 and a dielectric layer 140 . The P-type substrate 100 can be divided into a HVNMOSFET region and a HVPMOSFET region comprising a high voltage N-type MOSFET (NMOSFET) and a high voltage P-type MOSFET (PMOSFET), respectively. The doped regions 126 n , 128 n and the gate 102 are the source, the drain and the gate of the high voltage NMOSFET, and the doped regions 120 p , 118 p and the gate 104 are the source, the drain and the gate of the high voltage PMOSFET. The doped regions 116 p , 118 p and 120 p have p+ conductivity type and the doped regions 126 n , 128 n and 130 n have n+ conductivity type. However, the high voltage device in FIG. 1 may have the following drawbacks: 1. The high voltage device may have latch-up problem. More specifically, the doped region 120 p , the N-tub 124 n and the P-type substrate 100 may form the emitter, the base and the collector of a parasitic bipolar transistor, and the doped region 126 n , the P-type substrate 100 and the N-tub 124 n may form the emitter, the base and the collector of another parasitic bipolar transistor. When the current/gain product of the two bipolar transistors is greater than 1, the high voltage device cannot operate normally. 2. The foregoing high voltage PMOS and the high voltage NMOS are disposed on the P-type substrate 100 . Since the input voltage applied to the doped region 120 p is directly applied to the P-type substrate 100 , the input voltage is subjected to considerable limitations so that the operating range of the high voltage device is reduced. 3. In general, other semiconductor devices are also disposed on the P-type substrate 100 . However, none of the sides of the high voltage device have provided sufficient isolation. Therefore, mutual interference between the high voltage device and these semiconductor devices may occur. Since the operation of the CMOSFET may affect the operations of other semiconductor devices disposed above the substrate, the design must be improved. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a semiconductor device capable of minimizing input voltage limitation problem and preventing mutual interference with other semiconductor devices. The present invention is also directed to a CMOSFET capable of improving latch-up in the device. As embodied and broadly described herein, the present invention provides a CMOSFET including a substrate, a first epitaxial layer, a second epitaxial layer, a first sinker, a second sinker, a well, a first transistor, a second transistor, a first buried layer, a second buried layer and a deep trench isolation. The substrate has a first conductivity type. The first epitaxial layer has the first conductivity type and is disposed on the substrate. The second epitaxial layer has a second conductivity type and is disposed on the first epitaxial layer. The first sinker has the second conductivity type and is disposed in the second epitaxial layer. The first sinker extends from the first epitaxial layer to the upper surface of the second epitaxial layer. The first sinker separates a first region from the second epitaxial layer. The second sinker has the second conductivity type and is disposed in the second epitaxial layer. The second sinker extends from the first epitaxial layer to the upper surface of the second epitaxial layer. The second sinker separates a second region from the second epitaxial layer outside the first region. The well has the second conductivity type and is disposed inside the first region. The first transistor is disposed in the well and the second transistor is disposed in the second region. The first buried layer has the second conductivity type. The first buried layer is disposed between the first region and the first epitaxial layer and electrically connected to the first sinker. The second buried layer has the second conductivity type. The second buried layer is disposed between the second region and the first epitaxial layer and electrically connected to the second sinker. The deep trench isolation is disposed between the first region and the second region and extends from the substrate to the upper surface of the second epitaxial layer. In one embodiment of the present invention, the material of the foregoing deep trench isolation includes dielectric material, polysilicon, doped polysilicon, metal or titanium/titanium nitride/tungsten composite, for example. In one embodiment of the present invention, a metal silicide layer is also disposed between the foregoing deep trench isolation and the substrate. The material of the metal silicide layer includes titanium silicide, nickel silicide, cobalt silicide or tungsten silicide, for example. In one embodiment of the present invention, the dopant concentration of the foregoing first buried layer and the second buried layer is higher than the dopant concentration of the second epitaxial layer, for example. In one embodiment of the present invention, the foregoing first transistor and the second transistor are high voltage MOSFET, for example. In one embodiment of the present invention, the foregoing first conductivity type is P-type and the second conductivity type is N-type. In another embodiment of the present invention, the foregoing first conductivity type is N-type and the second conductivity type is P-type. In brief, the present invention with the aforementioned design is capable of preventing latch-up problem. Furthermore, the CMOSFET in the present invention can be effectively isolated from external devices and hence a wider input voltage range can be tolerated. It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. FIG. 1 is a schematic cross-sectional view of a conventional high voltage device. FIG. 2 is a schematic cross-sectional view of a CMOSFET according to a first embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. To improve the conventional CMOSFET, the CMOSFET is disposed in an epitaxial layer on a substrate. More specifically, the epitaxial layer may include a first epitaxial layer and a second epitaxial layer starting from the substrate. The first epitaxial layer and the substrate have the same conductivity type while the second epitaxial layer and the substrate have opposite conductivity types. The first epitaxial layer and the second epitaxial layer may provide a diode rectifying function to prevent carriers from injecting into the substrate. Furthermore, since the dopant concentration of the substrate may be greater than the first epitaxial layer and the substrate may be grounded, the substrate provides a lower impedance pathway for disposing the extra carriers. Therefore, the carrier is prevented from affecting other semiconductor devices on the substrate. In addition, the present invention uses two sinkers and two buried layers to separate the second epitaxial layer into two regions and disposes the two transistors of the CMOSFET in the two regions respectively. Through the foregoing design arrangement, the parasitic diode or parasitic transistor can be modified. On the other hand, adjusting the voltage of the buried layers can prevent the input voltage applied to the CMOSFET from being totally applied to the substrate. This can widen the operating range of the CMOSFET. Furthermore, by setting at least one deep trench isolation between the two regions, the latch-up problem is effectively avoided. In the following, an embodiment is used to describe in detail the aforementioned structure. FIG. 2 is a schematic cross-sectional view of a CMOSFET according to a first embodiment of the present invention. As shown in FIG. 2 , the CMOSFET in the present invention includes a substrate 200 , a first epitaxial layer 201 p , a second epitaxial layer 202 n , a first sinker 204 n , a second sinker 206 n , a well 208 p , a first transistor A 1 , a second transistor A 2 , a first buried layer 210 n , a second buried layer 212 n and a deep trench isolation 300 . In the present embodiment, the CMOSFET further includes isolations 214 , a dielectric layer 216 , interconnects 234 , 236 , 238 , 240 , 242 , 318 , 320 , 322 and 324 . However, the present invention does not have to be limited in this way. The first transistor A 1 and the second transistor A 2 can be any types of transistors. The first transistor A 1 and the second transistor A 2 may be a high voltage MOSFET including the LDMOSFET, for example. In the present embodiment, the first transistor A 1 and the second transistor A 2 are another kind of the high voltage MOSFET. The first transistor A 1 includes a gate 220 , a gate dielectric layer 222 , doped regions 226 p , 228 n , 230 n and 232 n . The second transistor A 2 includes a gate 306 , a gate dielectric layer 308 , doped regions 310 n , 312 p , 314 p and 316 p . In addition, the conductivity type of the foregoing components in FIG. 2 are labeled using P-sub, P-epi, N-epi, N, PBL, NBL, P-well, n+, p+, N-drift and P-drift so that those skilled in the art can easily understand. However, these labels by no means limit the scope of the present invention. In other words, the foregoing components may have the opposite conductivity types in another embodiment. Furthermore, in the present embodiment, the first conductivity type is P-type and the second conductivity type is N-type. However, in another embodiment, the first conductivity type may be N-type while the second conductivity type may be P-type. The substrate 200 has the first conductivity type. The first epitaxial layer 201 p has the first conductivity type and is disposed on the substrate 200 . The substrate 200 has a dopant concentration greater than that of the first epitaxial layer 201 p , for example. If the substrate 200 is grounded, then the substrate 200 can provide a low impedance path for disposing the extra carriers produced by the first transistor A 1 or the second transistor A 2 in an operation. Thus, these extra carriers are prevented from affecting other semiconductor device on the substrate 200 . The second epitaxial layer 202 n has the second conductivity type and is disposed on the first epitaxial layer 201 p . The second epitaxial layer 202 n and the first epitaxial layer 201 p together form a diode. When the first transistor A 1 and the second transistor A 2 are in operation, the rectifying function of this diode may prevent the carriers from injecting into the first epitaxial layer 201 p and the substrate 200 . The first sinker 204 n has the second conductivity type and is disposed in the second epitaxial layer 202 n . The first sinker 204 n extends from the first epitaxial layer 201 p to the upper surface of the second epitaxial layer 202 n and separates a first region R 1 from the second epitaxial layer 202 n . On the other hand, the interconnect 240 is disposed in the dielectric layer 216 and electrically connected to the first sinker 204 n . The well 208 p has the first conductivity type and is disposed in the first area R 1 . The first transistor A 1 is disposed in the well 208 p . The doped region 226 p of the first transistor A 1 has the first conductivity type and the doped regions 228 n , 230 n and 232 n of the first transistor A 1 has the second conductivity type. The doped regions 228 n , 230 n , 232 n are the source, the drain, the drift region of the first transistor A 1 respectively. The doped regions 228 n and 230 n are disposed on two sides of the gate 220 and the doped region 230 n is disposed in the doped region 232 n . Furthermore, the interconnects 234 , 238 and 236 are disposed in the dielectric layer 216 and electrically connected to the doped region 230 n , the gate 220 , and the doped regions 228 n and 226 p respectively. The second sinker 206 n has the second conductivity type and is disposed in the second epitaxial layer 202 n . The second sinker 206 n extends from the first epitaxial layer 201 p to the upper surface of the second epitaxial layer 202 n and separates a second region R 2 from the second epitaxial layer 202 n outside the first region R 1 . In addition, the interconnect 324 is disposed in the dielectric layer 216 and electrically connected to the second sinker 206 n . The second transistor A 2 is disposed in the second region R 2 . The doped region 310 n of the second transistor A 2 has the second conductivity type and the doped regions 312 p , 314 p and 316 p of the second transistor A 2 has the first conductivity type. The doped regions 312 p , 314 p , 316 p are the source, the drain and the drift region of the second transistor A 2 respectively. The doped regions 312 p and 314 p are disposed on the two sides of the gate 306 and the doped region 314 p is disposed in the doped region 316 p . Furthermore, the interconnects 318 , 322 and 320 are disposed in the dielectric layer 216 and electrically connected to the doped region 314 p , the gate 306 , and the doped regions 312 p and 310 n respectively. The first buried layer 210 n has the second conductivity type and is disposed between the first region R 1 and the first epitaxial layer 201 p . The first buried layer 210 n is electrically connected to the first sinker 204 n . The second buried layer 212 n has the second conductivity type and is disposed between the second region R 2 and the first epitaxial layer 201 p . The second buried layer 212 n is electrically connected to the second sinker 206 n . The first buried layer 210 n and the second buried layer 212 n are, for example, heavily doped regions. Furthermore, the dopant concentration of the first buried layer 210 n and the second buried layer 212 n are, for example, greater than the dopant concentration of the second epitaxial layer 202 n . With the provision of the first buried layer 210 n and the second buried layer 212 n , the input voltage of the first transistor A 1 and the second transistor A 2 will not be entirely applied to the substrate 200 . Thus, the acceptable range of the input voltage is increased. For example, if a high voltage is applied to the interconnect 234 or 320 , then the first buried layer 210 n and the second buried layer 208 n can avoid an electrical breakdown at the interface between the second epitaxial layer 202 n and the first epitaxial layer 201 p. Furthermore, when a high voltage is applied to the interconnect 234 , the potential of the interconnect 240 is, for example, lower than that of the interconnect 234 but higher than that of the interconnect 236 . Thus, the high voltage is able to directly applied to the interconnect 240 and further prevents an electrical breakdown at the interface between the second epitaxial layer 202 n and the first epitaxial layer 201 p . Similarly, when a high voltage is applied to the interconnect 320 , the potential of the interconnect 324 is, for example, lower than that of the interconnect 320 but higher than that of the interconnect 318 . Therefore, the high voltage is able to directly applied to the interconnect 324 and prevents an electrical breakdown at the interface between the second epitaxial layer 202 n and the first epitaxial layer 201 p . Consequently, a wider range of voltage can be applied to the interconnect 234 or the interconnect 320 . It is also obvious that a wider range of voltage can be applied to the interconnects 236 and 318 as well. All in all, the first sinker 204 n , the second sinker 206 n , the first buried layer 210 n and the second buried layer 212 n can absorb the extra carriers to prevent a latch-up with other semiconductor devices on the substrate 200 while the CMOSFET is in operation. In another embodiment, the input voltages of other semiconductor devices can be prevented from interfering with the operation of the CMOSFET by adjusting the voltage of the interconnects 240 and 324 . Furthermore, by setting up the first sinker 204 n , the second sinker 206 n , the first buried layer 210 n and the second buried layer 212 n , the parasitic diode structure that comprises the doped region 312 p , the second epitaxial layer 202 n , the first epitaxial layer 201 p , the substrate 200 and the doped region 228 n is modified so that latch-up problem is prevented. More specifically, the doped region 312 p , the second epitaxial layer 202 n in the second region R 2 and the substrate 200 together form the emitter, the base and the collector of a parasitic bipolar transistor, and the doped region 228 n , the substrate 200 and the second epitaxial layer 202 n in the second region R 2 together form the emitter, the base and the collector of another parasitic bipolar transistor. Since the first buried layer 210 n and the second buried layer 212 n can be heavily doped region, the dopant concentration of the foregoing base is increased. As a result, the current gain of the bipolar transistors is lowered. Moreover, the current gain can be changed to limit latch-up by adjusting the voltage of the interconnects 240 and 324 . The deep trench isolation 300 is disposed between the first region R 1 and the second region R 2 and extends from the substrate 200 to the upper surface of the second epitaxial layer 202 n as shown in FIG. 2 . However, the present invention does not limit the number of deep trench isolation 300 and the number of deep trench isolation 300 could be one to a few. The deep trench isolation 300 is formed from the dielectric layer 302 and the isolation material 304 , for example. The dielectric layer 302 is located between the isolation material 304 and the first epitaxial layer 201 p and between the isolation material 304 and the second epitaxial layer 202 n . The material of the dielectric layer 302 includes silicon oxide, for example. The material forming the isolation material 304 includes dielectric material, polysilicon, doped polysilicon, metal or a titanium/titanium nitride/tungsten composite structure, for example. If the isolation material 304 is not a dielectric material, then a metal silicide layer 305 might be disposed between the isolation material 304 and the substrate 200 for providing better conductivity between the isolation material 304 and the substrate 200 . The material forming the metal silicide layer 305 includes, for example, titanium silicide, nickel silicide, cobalt silicide or tungsten silicide. In addition, the present invention further includes an interconnect 242 electrically connected to the isolation material 304 . The dielectric layer 302 isolates the first transistor A 1 from the second transistor A 2 . Hence, the substrate 200 is the only remaining conductive path between the first transistor A 1 and the second transistor A 2 . Furthermore, by adjusting the voltage of the interconnect 242 , the deep trench isolation 300 may absorb extra carriers in the substrate 200 . By setting up the deep trench isolation 300 , the CMOSFET of the present invention can prevent latch-up. In the present embodiment, the CMOSFET of the present invention may further include a junction isolation 217 p for isolating the CMOSFET from other semiconductor devices even more. The junction isolation 217 p has the first conductivity type and locates between the CMOSFET and other semiconductor devices over the substrate 200 . The junction isolation 217 p comprises a buried layer 218 p and a well 219 p , for example. The buried layer 218 p extends from the first epitaxial layer 201 p to the second epitaxial layer 202 n , and the well 219 p extends from the buried layer 218 p to the upper surface of the second epitaxial layer 202 n . In the processing of the CMOSFET, the well 219 p and the well 208 p are formed simultaneously, for example. In summary, latch-up is effectively avoided with the foregoing setup according to the present invention. In addition, the CMOSFET of the present invention can be effectively isolated from other devices and permissible range of the input voltage can be increased. Moreover, because the first sinker, the second sinker and the deep trench isolation occupy only a small portion of the available substrate area, and the first buried layer and the second buried layer are located under the first transistor and the second transistor respectively, a higher level of integration can be achieved. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

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